The present application relates to semiconductor structures and methods of fabricating the same, and more particularly to contact structures with improved contact resistance and reliability and methods of forming the same.
Field Effect Transistors (FETs) are essential components of all modern electronic products. Generally, after a transistor is formed, electrical contacts are made to connect a source region, a drain region, and/or a gate region of the transistor to make the transistor fully functional. Typically, lithographic techniques are used to define contact openings in a dielectric material that surrounds the transistor for the electrical contacts. The contact openings are then filled with a metal filler to form electrical contacts. As FETs are scaled to smaller dimensions, increased contact resistance to the source region and the drain region (hereinafter collectively referred to as “source/drain regions”) jeopardizes device performance, especially for the 32 nm technology node and beyond. A liner silicide has been employed to reduce the contact resistance between the metal filler and the source/drain regions. For example, a NiPt silicide liner has been shown to provide good on-resistance (Ron) for both n-type FETs (nFETs) and p-type FETs (PFETs). However, since the NiPt liner from which the NiPt silicide liner is derived is not removed from sidewalls of the contact openings, Ni diffusion into the dielectric material surrounding the contact openings raises liability concerns. Therefore, there remains a need to develop contact structures with improved contact resistance and reliability.